1. Field of the Invention
The present invention relates to a fabrication process of a compound semiconductor device including two kinds of field effect transistors (FETs) of an enhancement (E) type and a depletion (D) type, which employs a compound semiconductor layer or a two-dimensional electron gas (2DEG) layer as channels.
2. Description of the Related Art
Compound semiconductor, typically GaAs, is characterized by superior electron mobility in comparison with Si. In the recent years, application of a hetero-junction FET (HJFET) utilizing a high electron mobility of 2DEG generated at an interface between stack of different kinds of compound semiconductor layers grown by epitaxial growth method, for digital integrated circuit have been actively developed. In particular, for high signal speed/power consumption performance ratio, such technology has been expected to be applied in a small-size computers, communication field and so forth.
Since mobility of p-type carrier is low in comparison with n-type in the compound semiconductor, only n-type is employed in the integrated circuit. Generally, the integrated circuit comprises two kinds of FETs, i.e. an E-type FET having a positive gate threshold voltage (V.sub.T) and a D-type FET having a negative gate threshold voltage. As a basic inverter circuit, a direct coupled FET logic (DCFL) is mainly employed. In this case, the E-type FET is used as a drive element and the D-type FET is used as a load element.
As a fabrication process of such FET, a selective etching recess method, in which a etching stop layer is provided within the epitaxial grown crystal layer for controlling an etching stop position, has been known.
Technical Study Report of Electronic Device, "Speeding of Short Gate HEMT IC with New Recess Gate Structure", Japan Electronic Information Communication Engineering Institute, ED89-133, pp 29-34 (1990) proposes a technology for improvement of performance of E-type FET (hereinafter, this proposal will be referred to as "first prior art). Hereinafter, the first prior art will be discussed with reference to FIGS. 1 to 3. It should be noted that, among these drawings, FIG. 3 shows the element structure as proposed in the above-identified report, and FIGS. 1 and 2 illustrate element structures as background for the element structure of FIG. 3.
FIG. 1 is a section of a normal recess-gate type FET. On a semi-insulative GaAs substrate 301, a channel layer (undoped GaAs) 303, an electron supply layer (n-type AlGaAs) 304, and a contact layer (n-type GaAs) 307 are deposited in order by epitaxial growth process. A gate electrode 314 is in contact with the electron supply layer 304 buried in the contact layer 307. On the contact layer 307 at both sides of the gate electrode 314, a source electrode 316 and a drain electrode 317 are formed.
In the shown structure, by increasing thickness of the contact layer 307, a source resistance R.sub.s can be lowered and a mutual conductance g.sub.m can be improved. However, on the other hand, when the thickness of the contact layer 307 is increased, contact area of the gate electrode 314 and the contact layer 307 is inherently increased to cause increasing of gate parasitic capacity. Also, in such case, gate leak current is increased to lower gate voltage and whereby lower margin of operation in the logic circuit. For reducing the gate parasitic capacity and for improving the gate voltage, the thickness of the contact layer 307 is to be reduced. However, in such case, source resistance R.sub.s is increased to lower the mutual conductance g.sub.m.
On the other hand, in the D-type FET, a structure as shown in FIG. 2, in which a gap 322 is defined by side etching of the contact layer 307 at both sides of the gate electrode 314 is employed for reduction of the source resistance R.sub.s and for improving gate parasitic capacity. However, if this structure is directly applied for the E-type FET, a depletion layer extending from the semiconductor surface of the gap 322 to a channel layer 303 is formed to cut the channel to make the FET inoperative.
Therefore, in the E-type element, there has been developed a structure which can improve both of the parasitic capacity and the gate voltage. The structure is a two-state recess structure of the element as illustrated in FIG. 3, shown in a form of cross-section.
In the E-type element, the contact layer is divided into an upper contact layer 307a and a lower contact layer 307b. In the upper contact layer 307a, a gap 322 is provided so that the gate electrode 314 may not contact with the upper contact layer 307a. On the other hand, the lower contact layer 307b is in contact with the side surface of the gate electrode 314. The layer thickness of the lower contact layer 307b is selected so that a depletion layer may not reach the channel layer 303. With this structure, the E-type element can operate. In the two-state recess structure, in comparison with the thickness of the lower contact layer 307b, the thickness of the upper contact layer 307a is sufficiently greater to make it possible to make the source resistance R.sub.s sufficiently small without causing degradation of the gate parasitic capacity and the gate voltage.
The E-type FET with the two-state recess structure is fabricated through the following process. At first, on the semi-insulative GaAs substrate 301, the undoped GaAs layer is formed as a channel layer 303, the n-type AlGaAs layer as the electron supply layer 304, the n-type GaAs layer as the lower contact layer 307b, an n-type AlGaAs layer as the etching stop layer 306, and n-type GaAs layer as the upper contact layer 307a are deposited in order by epitaxial growth method.
Then, an insulation layer (not shown) which serves as a spacer is formed on the deposited layers. Then, a photoresist layer (not shown) which has an opening above a gate portion is formed on the insulation layer. Then, the insulation layer is selectively etched with taking the photoresist layer as a mask.
Subsequently, by isotropic dry etching having selectivity for AlGaAs, the upper contact layer 307a is selectively etched to form a recess on the epitaxial substrate. At this time, by controlling over-etching amount, the size of the gap 322 is adjusted. Then, removing the etching stop layer 306, etching is performed for the lower contact layer 307b by a selective anisotropic dry etching employing a mixture gas of CCl.sub.2 F.sub.2 and He. At this time, selection ratio of AlGaAs and GaAs can be made greater than or equal to 200. Then, the gate electrode is formed by way of a lift off method.
On the other hand, Japanese Unexamined Patent Publication (Kokai) No. Heisei 2-148740 proposes a fabrication process for forming E-type and D-type elements on a common substrate (hereinafter, the proposed construction and the fabrication process in the above-identified publication will be referred to as "second prior art"). Hereinafter, the second prior art will be discussed with reference to FIGS. 4 to 7 which are sections showing the fabrication process proposed in Japanese Unexamined Patent Publication No. Heisei 2-148740.
(1) As shown in FIG. 4, by a molecular beam epitaxy (MBE) method or a metal organic chemical vapor deposition (MOCVD) method, an undoped GaAs layer as a channel layer 403 in a thickness of 500, an n-type AlGaAs layer as an electron supply layer 404 in a thickness of 30, an n-type GaAs layer as a threshold voltage controlling layer 405 for adjusting a gate threshold voltage in the depletion-type transistor in a thickness of 10, an n-type AlGaAs layer as a third etching stop layer 406c in a thickness of 5 nm, an n-type GaAs layer as a third contact layer 407c in a thickness of 15, an n-type AlGaAs layer as a second etching stop later 406b in a thickness of 5 nm, an n-type GaAs layer as a second contact layer 407b in a thickness of 60 nm, an n-type AlGaAs layer as a first etching stop layer 407a in a thickness of 5 nm and an n-type GaAs layer as a first contact layer 406a are grown on a semi-insulative GaAs substrate 401. Respective of n-type AlGaAs layers and n-type GaAs layers have a common donor density of 2.times.10.sup.18 cm.sup.-3.
Mesa etching is then performed by a wet etching method employing a hydrogen fluoride type etching liquid as enchant for isolation between elements. Also, element isolation may also be performed by ion implantation method.
The first contact layer 407a (n-type GaAs) and first etching stop layer 406a (n-type AlGaAs) in the E-type element are selectively etched with taking the photoresist as a mask to form a recess A.
(2) Subsequently, as shown in FIG. 5, as a SiO.sub.2 layer as an insulation layer 410 is grown on the entire surface in a thickness of approximately 300 nm. With taking the photoresist as a mask, opening is formed in the insulation layer 410 to form ohmic source electrodes 416 and 418 and drain electrodes 417 and 419 by a lift off method.
(3) Subsequently, as shown in FIG. 6, a photoresist layer 408 having openings 408E and 408D for forming respective gate electrodes in the E-type and D-type element regions is formed. With taking the photoresist layer 408 as a mask, openings 410E and 410D are formed in the insulation layer 410 by a wet etching method employing a hydrogen fluoride type etching liquid or a RIE method employing a carbon fluoride type gas.
Thereafter, by application of RIE method under the condition of etching gas: CC1.sub.2 F.sub.2, pressure: 20 Pa, self-bias voltage: 30 V, isotropic etching is performed for n-type GaAs layers (second contact layer 407b and the first contact layer 407a) of respective of the E-type and D-type elements. At this time, the n-type AlGaAs layers beneath respective n-type GaAs layers 407b and 407a (i.e. the second etching stop layer 406b and the first etching stop layer 406a) serve as stoppers.
Subsequently, by etching the etching stop layers 406b and 406a exposed by hydrogen fluoride type enchant, the n-type GaAs layers (third contact layer 407c and the second contact later 407b) below the etching stop layers 406b and 406a are exposed.
Thereafter, by application of RIE method under the condition of etching gas: CC1.sub.2 F.sub.2, pressure 20 Pa and self-bias voltage: 30 V, isotropic dry etching is performed for the third contact layer 407c and the second contact layer 407b to expose the surfaces of the n-type AlGaAs layers (third etching stop layer 406c and the second etching stop later 406b) respectively located below the third contact layer 407c and the second contact layer 407b. Subsequently, similarly to the former case set forth above, by performing etching for the third and second etching stop layers 406c and 406b employing the hydrogen fluoride type etchant, the surfaces of the n-type GaAs layers (threshold valve controlling layer 405 and third contact layer 407c) located below the third and second etching stop layers 406c and 406b are exposed.
Thereafter, application of RIE method under a condition of etching gas: CC1.sub.2 F.sub.2, lowered pressure: 5 Pa, and elevated self-bias: 100 V, anisotropic dry etching is performed for the threshold valve controlling layer 405 and third contact layer 407c to form gate openings 411 and 412. Etching is stopped at the n-type AlGaAs layer (electron supply layer 404 and third etching stop layer 406c) respectively located below threshold valve controlling layer 405 and third contact layer 407c (FIG. 6).
(4) Subsequently, as shown in FIG. 7, by employing the remained photoresist layer 408, Schottky junction type gate electrodes 414 and 415 are formed by aluminum in the thickness of 400 nm in respective gate openings 411 and 412 to complete fabrication of the E-type and D-type elements.
Through etching of the epitaxially deposited layers, in the E-type element region, etching of the crystal layer is advanced relative to the D-type element region in the extent of the recess A formed in the initial process of (1). Therefore, finally, the electron supply layer 404 is exposed in the E-type element, whereas the third etching stop layer 406c above the threshold valve controlling layer 405 is exposed in the D-type element region.
When the gate electrodes are formed, respective gate electrodes of the E-type and D-type elements are buried within the thin threshold valve controlling layer 405 and the third contact layer 407c. Therefore, reduction of the source resistance R.sub.s of the E-type element and improvement in the gate voltage at the D-type element. Furthermore, a gate parasitic capacitor can be reduced.
On the other hand, the task of the compound semiconductor integrated circuit device is, in formation of the E-type and D-type elements on the common substrate:
(1) to assure to have sufficient mutual conductance g.sub.m by reducing the source resistance; PA1 (2) to assure to provide sufficient tolerance voltage, such as gate breakdown voltage; PA1 (3) to reduce the parasitic capacity; and PA1 (4) to be able to be fabricated easily and stably. PA1 a first step of sequentially growing a first conductive semiconductor layer group, a second conductive semiconductor layer group and a low resistance conductive semiconductor layer on a semi-insulative semiconductor substrate in order; PA1 a second step of forming a first insulation layer on the low resistance conductive semiconductor layer and forming first and second gate openings by selectively etching the first insulation layer; PA1 a third step of selectively etching the low resistance conductive semiconductor layer exposed by the first and second gate openings formed in the first insulation layer to expose the surface of the second conductive semiconductor layer group to form third and fourth gate openings continuous to the first and second gate openings; PA1 a fourth step of forming a side wall insulation layer in the side wall of the first to fourth gate openings by depositing second insulation layer on entire surface and by etching back the second insulation layer; PA1 a fifth step of selectively etching the second conductive semiconductor layer group exposed through the third gate opening with masking the second and fourth gate openings to expose the surface of the first conductive semiconductor layer group to form a fifth gate opening continuous to the third gate opening; and PA1 a sixth step of forming a first gate electrode contacting with the surface of the first conductive semiconductor layer group via the first, third and fifth gate openings and with the side surface of the second conductive semiconductor layer group, and a second gate electrode contacting with the second conductive semiconductor layer group via the second and fourth gate openings. PA1 the fifth step may include a selective etching step for the etching stop layer and an isotropic dry etching step for the threshold voltage controlling layer. In the alternative, the fifth step may include a selective etching step for the etching stop layer and an etching step for the threshold voltage controlling layer performed by generating a plasma by an electron cyclotron resonance.
are to be satisfied. However, in the fabrication process of the foregoing (1), (2) and (3), the number of crystal for achieving (1), (2) and (3) becomes nine and the structure becomes more complicate. Furthermore, after initial etching for the E-type element region, it becomes necessary to perform crystal dry etching for three times. Therefore, large number of steps becomes large to make the fabrication process more complicate.
Also, in the foregoing first and second prior arts, after isotropic crystal etching, the crystal surfaces located way from the mask are treated by chemical etching by the anisotropic etching. However, gas component of Cl to be employed in the crystal etching has a chemically high tendency of isotropic etching, anisotropy cannot be enhanced unless the gas pressure is lowered to raise the self-bias voltage. However, in such measure, strong damage may be given for the lower crystal layer to lower carrier density and mobility.
On the other hand, by lightening anisotropy, etching can be progressed in the lateral direction to make the gate electrode and the contact layer kept isolated and thus the desired buried gate structure cannot be achieved, and the source resistance is increased to lower the mutual conductance g.sub.m. Furthermore, the etching condition may be varied detecting upon the pattern density, configuration and so forth, precision of the distance between the gate electrode and the contact layer region in the case where the gate cannot be buried becomes insufficient, to make fluctuation of characteristics in the wafer or between wafers significant.
Furthermore, in the conventional fabrication process, crystal dry etching is progressed with taking the gate opening pattern of the initially formed photoresist layer as the mask, and the photoresist layer is used until lift-off formation of the gate electrode. However, the photoresist layer is etched out to widen the opening of the photoresist layer, final gate length dimension becomes greater to lower the precision. Also, for unstability of the gate length, it is undesirable in view of high frequency characteristics.